(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of reducing via poisoning in low-k dielectric materials through the use of a protective metal layer.
(2) Description of the Related Art
Low-k dielectric materials are favored in the semiconductor industry because they have low dielectric constant (k), and therefore, are useful in reducing the resistance-capacitance (RC) delay, or, time constant, of the circuitry in which they are used. However, low-k dielectrics are usually porous, and can trap moisture and other contaminants, thereby giving rise to poisoned interconnects, or vias, as is known in the art, during the process of manufacturing integrated circuit chips. The present invention discloses a method of preventing such poisoned vias.
Copper dual damascene is a preferred interconnect because, as is well known in the art, copper has lower resistivity than the commonly used aluminum and, therefore contributes to lower RC delay. The damascene process also provides a better control of the metal line geometries, as described below, and therefore improves further the RC characteristics of the lines. However, if the damascene structure is not properly protected during forming of the contact and via holes, the holes can be “poisoned” due to outgassing from the insulative layers, and/or due to the hydrophobic nature of the insulative layers. A poisoned contact hole (reaching the substrate), or a poisoned via hole (connecting different metallized layers) can give rise to voids, cavities for contaminants to enter, poor interfaces between contacting conductors, and, hence, poor connections between interconnects. It is disclosed later in the embodiments of the present invention a method of providing a protective layer over the insulative low-k dielectric to prevent entrapment of any contaminants which may give rise to poisoning of the interconnects. The method is especially well-suited for damascene interconnects.
Copper dual damascene process is a well-known technique for forming interconnections in semiconductor devices. It is especially well suited for Ultra Large Scale Integrated (ULSI) circuit technology where more and more devices are being packed into the same or smaller areas in a semiconductor substrate. As the feature sizes get smaller, the smaller geometries result in higher electrical resistances, which in turn degrade circuit performance. As will be described more fully later, damascene process provides a more exact dimensional control over small geometries, while copper, as the metallization material, provides better electrical characteristics.
The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, trenches and holes in appropriate locations in the trenches are formed in an insulative material by etching, which are then filled with metal. Metal in trenches form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or trenches, are formed in an insulative layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the trenches of a single damascene, hole openings are also formed at appropriate places in the trench further into the insulative layer. The resulting composite structure of trenches and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process shown in FIG. 1a, two insulative layers (120) and (130) are formed on a substrate (100) with an intervening etch-stop layer (125). Substrate (100) is provided with metal layer (110) and a barrier layer (115). Metal layer can be the commonly used aluminum or copper, while the barrier can be an oxide layer. A desired trench or trench pattern (150) is first etched into the upper insulative material (130) using conventional photolithographic methods and photoresist (140). The etching stops on etch-stop layer (125). Next, a second photoresist layer (160) is formed over the substrate, thus filling the trench opening (150), and patterned with hole opening (170), as shown in FIG. 1b. The hole pattern is then etched into the lower insulative layer (120) as shown in FIG. 1c and photoresist removed, thus forming the dual damascene structure shown in FIG. 1f. 
Or, the order in which the trench and the hole are formed can be reversed. Thus, the upper insulative layer (130) is first etched, or patterned, with hole (170), as shown in FIG. 1d. The hole pattern is also formed into etch-stop layer (125). Then, the upper layer is etched to form trench (150) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (120), as shown in FIG. 1e. It will be noted that the etch-stop layer stops the etching of the trench into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (180), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in FIG. 1f. 
However, when trench (150), or hole (170) openings are formed through the insulative layers (120) and (130) as shown in FIGS. 1b-1e, moisture (190) is absorbed from the atmosphere by the exposed dielectric layers on the sidewalls of the openings. After copper (180) is deposited, moisture (190) is then released from the dielectric layers. This moisture diffuses into the metal causing poisoned via/contact metallurgy.
A method for forming a dual damascene structure with a low-k dielectric material is disclosed in U.S. Pat. No. 5,916,823 as cited by Lou, et al., with the steps of: forming a liner oxide layer onto the substrate; forming a first low k dielectric layer atop the liner oxide layer; forming a cap oxide layer atop the first low-k dielectric layer; forming a first nitride layer atop the cap oxide layer; patterning and etching the first nitride layer to form a contact opening; forming a second low-k dielectric layer into the contact opening and atop the first nitride layer; forming a second nitride layer atop the second low-k dielectric layer; forming a photoresist layer atop the second nitride layer; patterning and developing the photoresist layer to expose a trench opening, wherein the trench opening is of different dimension than the contact opening; forming a dual damascene opening by etching the second nitride layer and the second low-k dielectric layer, using the photoresist layer as a mask, and by etching the cap oxide layer, the first low-k dielectric layer and the liner oxide layer, using the first nitride layer as a mask; stripping the photoresist layer; forming oxide side spacers into the dual damascene opening; and depositing a conductive layer into the dual damascene opening.
A different dual damascene structure with a dielectric layer, and process for manufacturing it, are described in U.S. Pat. No. 6,140,220 by Lin where a via bole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. The process relies upon the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.
Still another method of forming a dual damascene structure is disclosed in U.S. Pat. No. 6,074,942 by Lou. The method comprises the steps of: forming an insulating layer on said substrate; forming a nitride layer over said insulating layer; forming a cap oxide layer over said nitride layer; patterning and etching said insulating layer, nitride layer, and cap oxide layer to correspond to the location of said contacts; patterning and etching said nitride layer and said cap oxide layer to correspond to the pattern of said interconnects; and performing a reflow step.
It is disclosed in the present invention a different method of forming a dual damascene interconnect where the low-k dielectric layers are protected by a metal layer in order to prevent the occurrence of poisoned vias.